OMAP3530ECBBA datasheet(171/264 Pages) TI1

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gpmc_fclk

gpmc_clk

gpmc_ncsx

gpmc_a[26:17]

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

gpmc_a[16:1]_d[15:0]

gpmc_waitx

gpmc_io_dir

Address(MSB)

Valid Address(LSB)

DataOUT

OUT

FA0

FA1

FA9

FA10

FA3

FA25

FA29

FA12

FA27

FA28

FA0

FA10

030-031

6.4.1.3 GPMC/NAND Flash Interface Timing

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing

Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see

Figure 6-13 through Figure 6-16) and electrical characteristic conditions.

Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

1.8

Input signal fall time

1.8

Output Conditions

CLOAD

Output load capacitance

15.94

Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters(1)(2)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI1

Maximum output data generation delay from

6.5

9.1

13.7

internal functional clock

GNFI2

Maximum input data capture delay by internal

5.6

8.1

functional clock

(1)

Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2)

Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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