OMAP3530ECBBA datasheet(215/264 Pages) TI1

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6.6.3

Multiport Full-Speed Universal Serial Bus (USB) Interface

6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

The OMAP3530/25 processor provides three USB ports working in full- and low-speed data transactions

(up to 12Mbit/s).

Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports:

• 6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode

• 4-pin bidirectional mode

• 3-pin bidirectional mode

Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-43).

Table 6-77. Low-/Full-Speed USB Timing Conditions – Unidirectional Standard 6-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.0

Input signal fall time

2.0

Output Conditions

CLOAD

Output load capacitance

15.0

Table 6-78. Low-/Full-Speed USB Timing Requirements – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSU1

td(Vp,Vm)

Time duration, mmx_rxdp and mmx_rxdm low together during

14.0

transition

FSU2

td(Vp,Vm)

Time duration, mmx_rxdp and mmx_rxdm high together during

8.0

transition

FSU3

td(RCVU0)

Time duration, mmx_rrxcv undefine during a single end 0

14.0

(mmx_rxdp and mmx_rxdm low together)

FSU4

td(RCVU1)

Time duration, mmx_rxrcv undefine during a single end 1

8.0

(mmx_rxdp and mmx_rxdm high together)

Table 6-79. Low-/Full-Speed USB Switching Characteristics – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSU5

td(TXENL-DATV)

Delay time, mmx_txen_n low to mmx_txdat valid

81.8

84.8

81.8

84.8

FSU6

td(TXENL-SE0V)

Delay time, mmx_txen_n low to mmx_txse0 valid

81.8

84.8

81.8

84.8

FSU7

ts(DAT-SE0)

Skew between mmx_txdat and mmx_txse0 transition

1.5

FSU8

td(DATI-TXENH)

Delay time, mmx_txdat invalid to mmx_txen_n high

81.8

FSU9

td(SE0I-TXENH)

Delay time, mmx_txse0 invalid to mmx_txen_n high

81.8

tR(do)

Rise time, mmx_txen_n

4.0

tF(do)

Fall time, mmx_txen_n

4.0

tR(do)

Rise time, mmx_txdat

4.0

tF(do)

Fall time, mmx_txdat

4.0

tR(do)

Rise time, mmx_txse0

4.0

tF(do)

Fall time, mmx_txse0

4.0

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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