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OMAP3530ECBBA 데이터시트(PDF) 247 Page - Texas Instruments

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부품명 OMAP3530ECBBA
상세설명  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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OMAP3530ECBBA 데이터시트(HTML) 247 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SD2
tW(clkL)
Typical pulse duration, output clk low
Y(5)*PO(4)
Y(5)*PO(4)
ns
tdc(clk)
Duty cycle error, output clk
2083.3
4166.7
ps
tj(clk)
Jitter standard deviation(6), output clk
200
200
ps
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc1_cmd transition
SD6
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc1_datx transition
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc1_cmd transition
SD6
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc1_datx transition
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc2_cmd transition
SD6
td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc2_datx transition
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
SD5
td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc3_cmd transition
SD6
td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
6.1
35.5
6.3
77
ns
mmc3_datx transition
(5)
The Y parameter is defined as shown in Table 6-141.
(6)
The jitter probability density can be approximated by a Gaussian function.
Table 6-140. X Parameter
CLKD
X
1 or Even
0.5
Odd
(trunk[CLKD/2]+1)/CLKD
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
247



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