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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCM1606E/2K 데이터시트(PDF) 8 Page - Texas Instruments |
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PCM1606E/2K 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 28 page  PCM1606 SLES014B − OCTOBER 2001 − REVISED AUGUST 2002 8 www.ti.com timing requirements (continued) DATA1, DATA2, DATA3 t(BCH) 1.4 V 1.4 V 1.4 V BCK LRCK t(BCL) t(LB) t(BCY) t(BL) tsu(D) th(D) PARAMETER MIN MAX UNIT t(BCY) BCK pulse cycle time 32 fS / 48 fS / 64 fS† t(BCH) BCK high-level time 35 ns t(BCL) BCK low-level time 35 ns t(BL) BCK rising edge to LRCK edge 10 ns t(LB) LRCK falling edge to BCK rising edge 10 ns tsu(D) DATA setup time 10 ns th(D) DATA hold time 10 ns † fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.) Figure 3. Audio Interface Timing Table 3. Bit Clock Rates for TDM Format Sampling Frequencies SAMPLING SYSTEM CLOCK FREQUENCY (fSCKI) (MHz) SAMPLING FREQUENCY 128 fS 256 fS 512 fS 8 kHz — 2.048 4.096 16 kHz — 4.096 8.192 32 kHz — 8.192 16.384 44.1 kHz — 11.2896 22.5792 48 kHz — 12.288 24.576 96 kHz — 24.576 49.152 192 kHz 24.576 See Note 7 See Note 7 NOTE 7: This bit clock is not supported for the given sampling frequency. |
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