STM32F372R8 datasheet(16/128 Pages) STMICROELECTRONICS

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Functional overview

STM32F37x

16/128

Doc ID 022691 Rev 3

Do not reconfigure GPIO pins which are not present on 48 and 64 pin packages to the

analog mode. Additional current consumption in the range of tens of µA per pin can be

observed if VDDA is higher than VDDIO.

3.10

Direct memory access (DMA)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management, avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger

support for each channel. Configuration is done by software and transfer sizes between

source and destination are independent.

The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC,

SDADCs, general-purpose timers.

3.11

Interrupts and events

3.11.1

Nested vectored interrupt controller (NVIC)

The STM32F37x devices embed a nested vectored interrupt controller (NVIC) able to

handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

●

Closely coupled NVIC gives low latency interrupt processing

●

Interrupt entry vector table address passed directly to the core

●

Closely coupled NVIC core interface

●

Allows early processing of interrupts

●

Processing of late arriving higher priority interrupts

●

Support for tail chaining

●

Processor state automatically saved

●

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.11.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 29 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 84

GPIOs can be connected to the 16 external interrupt lines.

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