STM32F372VC datasheet(100/128 Pages) STMICROELECTRONICS

100 / 128 page

Electrical characteristics

STM32F37x

100/128

Doc ID 022691 Rev 3

Figure 31.

12-bit buffered /non-buffered DAC

The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

Offset(3)

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

VREF+/2)

±10

±3

LSB

Given for the DAC in 10-bit at VREF+

= 3.6 V

±12

LSB

Given for the DAC in 12-bit at VREF+

= 3.6 V

Gain

error(3)

Gain error

±0.5

Given for the DAC in 12bit

configuration

tSETTLING

(3)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±1LSB

-3

µs CLOAD  50 pF, RLOAD  5 k

Update

rate(3)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s CLOAD  50 pF, RLOAD  5 k

tWAKEUP

(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

µs

CLOAD  50 pF, RLOAD  5 k

input code between lowest and

highest possible ones.

PSRR+ (1)

Power supply rejection ratio

(to VDDA) (static DC

measurement

--67

-40

dB No RLOAD, CLOAD = 50 pF

Guaranteed by design, not tested in production.

Quiescent mode refers to the state of the DAC keeping a steady value on the output, so no dynamic consumption is

involved.

Guaranteed by characterization, not tested in production.

Table 63.

DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

R LOAD

C LOAD

Buffered/Non-buffered DAC

DACx_OUT

Buffer(1)

12-bit

digital to

analog

converter

ai17157

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