CYUSB301X_13 datasheet(8/45 Pages) CYPRESS

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CYUSB301X

Document Number: 001-52136 Rev. *N

Page 8 of 45

JTAG Interface

FX3’s JTAG interface has a standard five-pin interface to connect

to a JTAG debugger in order to debug firmware through the

CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the FX3 application development.

Other Interfaces

FX3 supports the following serial peripherals:

■ UART

■ I

■ SPI

The SPI, UART, and I2S interfaces are multiplexed on the serial

peripheral port.

The CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit

Data Bus Width) on page 15 shows details of how these inter-

faces are multiplexed. Note that when GPIF II is configured for a

32-bit data bus width (CYUSB3012 and CYUSB3014), only the

UART interface is available on GPIO[53] to GPIO[56].

UART Interface

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Table 1.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3's UART only transmits data when the CTS

input is asserted. In addition to this, FX3’s UART asserts the RTS

output signal, when it is ready to receive data.

I2C Interface

FX3’s I2C interface is compatible with the I2C Bus Specification

Revision 3. This I2C interface is capable of operating only as I2C

master; therefore, it may be used to communicate with other I2C

slave devices. For example, FX3 may boot from an EEPROM

connected to the I2C interface, as a selectable boot option.

FX3’s I2C Master Controller also supports multi-master mode

functionality.

The power supply for the I2C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

gives the I2C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I2C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I2C controller supports the clock-stretching

feature to enable slower devices to exercise flow control.

The I2C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

I2S Interface

FX3 has an I2S port to support external audio codec devices.

FX3 functions as I2S Master as transmitter only. The I2S interface

consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output

on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

The sampling frequencies supported by the I2S interface are

32 kHz, 44.1 kHz, and 48 kHz.

SPI Interface

FX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 36 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Table 1. UART Interface Signals

Signal

Description

Output signal

Input signal

CTS

Flow control

RTS

Flow control

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