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Am79C940BVCW 데이터시트(PDF) 12 Page - Rochester Electronics

부품명 Am79C940BVCW
상세설명  Media Access Controller for Ethernet (MACE) 84-pin PLCC and 100-pin PQFP Packages
PDF  13 Pages
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제조업체  ROCHESTER [Rochester Electronics]
홈페이지  http://www.rocelec.com/
Logo ROCHESTER - Rochester Electronics

Am79C940BVCW 데이터시트(HTML) 12 Page - Rochester Electronics

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79C940
Specification Number 79C940B-CI (A) Rev C
Page 12 of 13
95
AC CHARACTERISTICS (continued)
Note:
1. Not tested but data available upon request.
No.
Parameter
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
GPSI Clock Timing
17
tSTDC
STDCLK period
99
101
18
tSTDCL
STDCLK low pulse width
See Note 1
45
19
tSTDCH
STDCLK high pulse width
45
20
tSTDCR
STDCLK rise time
See Note 1
5
21
tSTDCF
STDCLK fall time
See Note 1
5
22
tSRDC
SRDCLK period
85
115
23
tSRDCH
SRDCLK HIGH pulse width
38
24
tSRDCL
SRDCLK LOW pulse width
38
25
tSRDCR
SRDCLK rise time
See Note 1
5
26
tSRDCF
SRDCLK fall time
See Note 1
5
GPSI Timing
70
tTXEND
STDCLK↑ delay to TXEN↑
(CL = 50 pF)
70
71
tTXENH
TXEN hold time from STDCLK↑
(CL = 50 pF)
5
72
tTXDD
STDCLK↑ delay to TXDAT+ change (CL = 50 pF)
70
73
tTXDH
TXDAT+ hold time from STDCLK↑ (CL = 50 pF)
5
74
tRXDR
RXDAT rise time
See Note 1
8
75
tRXDF
RXDAT fall time
See Note 1
8
76
tRXDH
RXDAT hold time (SRDCLK↑ to
RXDAT change)
25
77
tRXDS
RXDAT setup time (RXDAT stable
to SRDCLK↑)
0
78
tCRSL
RXCRS low time
tSTDC + 20
79
tCLSHI
CLSN high time
tSTDC + 30
80
tTXH
TXEN or TXDAT± hold time from
CLSN↑
32*tSTDC
96*tSTDC
81
tCRSH
RXCRS hold time from SRDCLK↑
0
EADI Feature Timing
85
tDSFBDR
SRDCLK↓ delay to SF/BD↑
20
86
tDSFBDF
SRDCLK↓ delay to SF/BD↑
20
87
tEAMRIS
EAM/R invalid setup prior to
SRDCLK↓ after SFD
–150
88
tEAMS
EAM setup to SRDCLK↓ at bit 6 of
Source Address byte 1 (match
packet)
0
89
tEAMRL
EAM/R low time
200
90
tSFBDHIH
SF/BD high hold from last
SRDCLK↓
100
91
tEARS
EAR setup SRDCLK↓ at bit 6 of
message byte 64
(reject normal packet)
0
TABLE 5
SPECIFICATION NUMBER: 79C940-CI (A) REV -
Page 12 of 13



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