전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

AD5764CSUZ 데이터시트(PDF) 22 Page - Analog Devices

부품명 AD5764CSUZ
상세설명  Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD5764CSUZ 데이터시트(HTML) 22 Page - Analog Devices

Back Button AD5764CSUZ Datasheet HTML 18Page - Analog Devices AD5764CSUZ Datasheet HTML 19Page - Analog Devices AD5764CSUZ Datasheet HTML 20Page - Analog Devices AD5764CSUZ Datasheet HTML 21Page - Analog Devices AD5764CSUZ Datasheet HTML 22Page - Analog Devices AD5764CSUZ Datasheet HTML 23Page - Analog Devices AD5764CSUZ Datasheet HTML 24Page - Analog Devices AD5764CSUZ Datasheet HTML 25Page - Analog Devices AD5764CSUZ Datasheet HTML 26Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 28 page
background image
AD5764
Data Sheet
Rev. F | Page 22 of 28
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits
to 100. The DAC address bits select with which DAC channel
the data transfer is to take place (see Table 10). The fine gain
register is a 6-bit register and allows the user to adjust the gain
of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB
increments, as shown in Table 16 and Table 17. The adjustment
is made to both the positive full-scale points and the negative
full-scale points simultaneously, each point being adjusted by ½
of one step. The fine gain register coding is twos complement.
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to
101. The DAC address bits select with which DAC channel the
data transfer is to take place (see Table 10). The AD5764 offset
register is an 8-bit register and allows the user to adjust the offset
of each channel by −16 LSBs to +15.875 LSBs in increments of
⅛ LSB, as shown in Table 18 and Table 19. The offset register
coding is twos complement.
Table 16. Programming the Fine Gain Register Bit Map
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+31 LSBs
0
1
1
1
1
1
+30 LSBs
0
1
1
1
1
0
…
…
…
…
…
…
…
+2 LSBs
0
0
0
0
1
0
+1 LSB
0
0
0
0
0
1
No Adjustment (Default)
0
0
0
0
0
0
−1 LSB
1
1
1
1
1
1
−2 LSBs
1
1
1
1
1
0
…
…
…
…
…
…
…
−31 LSBs
1
0
0
0
0
1
−32 LSBs
1
0
0
0
0
0
Table 18. Programming the Offset Register Bit Map
REG2
REG1
REG0
A2
A1
A0
DB15:DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
DAC address
Don’t care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Table 19. AD5764 Offset Register Options
Offset Adjustment
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
+15.875 LSBs
0
1
1
1
1
1
1
1
+15.75 LSBs
0
1
1
1
1
1
1
0
…
…
…
…
…
…
…
…
…
+0.25 LSBs
0
0
0
0
0
0
1
0
+0.125 LSBs
0
0
0
0
0
0
0
1
No Adjustment (Default)
0
0
0
0
0
0
0
0
−0.125 LSBs
1
1
1
1
1
1
1
1
−0.25 LSBs
1
1
1
1
1
1
1
0
…
…
…
…
…
…
…
…
…
−15.875 LSBs
1
0
0
0
0
0
0
1
−16 LSBs
1
0
0
0
0
0
0
0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com