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AD5544BCPZ-R2 데이터시트(PDF) 16 Page - Analog Devices

부품명 AD5544BCPZ-R2
상세설명  Quad, Current-Output, Serial-Input 16-/14-Bit DACs
PDF  24 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD5544BCPZ-R2 데이터시트(HTML) 16 Page - Analog Devices

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AD5544/AD5554
Data Sheet
Rev. G | Page 16 of 24
TRUTH TABLES
Table 8. AD55441 Control Logic Truth Table
CS
CLK
LDAC
RS
MSB2
Serial Shift Register Function3
Input Register Function
DAC Register
High
X
High
High
X
No effect
Latched
Latched
Low
Low
High
High
X
No effect
Latched
Latched
Low
￪+3
High
High
X
Shift register data advanced one bit
Latched
Latched
Low
High
High
High
X
No effect
Latched
Latched
￪+3
Low
High
High
X
No effect
Selected DAC updated with
current shift register contents4
Latched
High
X
Low
High
X
No effect
Latched
Transparent
High
X
High
High
X
No effect
Latched
Latched
High
X
￪+3
High
X
No effect
Latched
Latched
High
X
High
Low
0
No effect
Latched data = 0x0000
Latched data = 0x0000
High
X
High
Low
High
No effect
Latched data = 0x8000
Latched data = 0x8000
1
For the AD5544, data appears at the SDO pin 19 clock pulses after input at the SDI pin.
2
X = don’t care.
3
￪ +is a positive logic transition.
4
At power-on, both the input register and the DAC register are loaded with all 0s.
Table 9. AD55541 Control Logic Truth Table
CS
CLK
LDAC
RS
MSB2
Serial Shift Register Function3
Input Register Function3
DAC Register
High
X
High
High
X
No effect
Latched
Latched
Low
L
High
High
X
No effect
Latched
Latched
Low
￪+3
High
High
X
Shift register data advanced one bit
Latched
Latched
Low
High
High
High
X
No effect
Latched
Latched
￪+3
Low
High
High
X
No effect
Selected DAC updated with
current shift register contents4
Latched
High
X
Low
High
X
No effect
Latched
Transparent
High
X
High
High
X
No effect
Latched
Latched
High
X
￪+3
High
X
No effect
Latched
Latched
High
X
High
Low
0
No effect
Latched data = 0x0000
Latched data = 0x0000
High
X
High
Low
High
No effect
Latched data = 0x2000
Latched data = 0x2000
1
For the AD5554, data appears at the SDO pin 17 clock pulses after input at the SDI pin.
2
X = don’t care.
3
￪ +is a positive logic transition.
4
At power-on, both the input register and the DAC register are loaded with all 0s.



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