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AD9776-EB 데이터시트(PDF) 3 Page - Analog Devices |
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AD9776-EB 데이터시트(HTML) 3 Page - Analog Devices |
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3 / 56 page ![]() AD9776/AD9778/AD9779 Rev. A | Page 3 of 56 FUNCTIONAL BLOCK DIAGRAM 10 10 10 10 CLOCK GENERATION/DISTRIBUTION DATA ASSEMBLER DIGITAL CONTROLLER 2× 2× SYNC1 CLOCK MULTIPLIER 2×/4×/8× 16-BIT IDAC CLK+ CLK– IOUT1_P IOUT1_N AUX1_P AUX1_N AUX2_P AUX2_N IOUT2_P IOUT2_N GAIN GAIN GAIN GAIN 16-BIT QDAC 2× SYNC1 I LATCH DELAY LINE Q LATCH P2D(15:0) P1D(15:0) SYNC_O SYNC_I DATACLK_OUT 2× 2× 2× n × fDAC/8 n = 0, 1, 2 ... 7 POWER-ON RESET SERIAL PERIPHERAL INTERFACE VREF I120 DELAY LINE Figure 2. Functional Block Diagram |
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