AD5204BRUZ100-R7 datasheet(7/20 Pages) AD

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AD5204/AD5206

Rev. C | Page 7 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

VDD 6

SHDN

SDI

CLK

SDO 10

VSS 11

NC 12

AD5204

TOP VIEW

(Not to Scale)

NC = NO CONNECT

Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration

Table 3. AD5204 SOIC/TSSOP/PDIP Pin Function Descriptions

Pin No.

Name

Description

1, 2, 12

Not Connected.

GND

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address

bits, and then it is loaded into the target RDAC latch.

Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.

VDD

Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.

SHDN

Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.

SDI

Serial Data Input. Data is input MSB first.

CLK

Serial Clock Input. This pin is positive edge triggered.

SDO

Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.

VSS

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.

Terminal B RDAC 3.

Wiper RDAC 3. Address = 0102.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 0002.

Terminal A RDAC 1.

Terminal A RDAC 2.

Wiper RDAC 2. Address = 0012.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 0112.

Terminal B RDAC 4.

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