CDC3RL02

SCHS371 – NOVEMBER 2009

www.ti.com

Output Stage

Each output drives 1.8-V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within 1

to 5ns with load capacitance between 10 pF and 50 pF. Fast slew rates introduce EMI into the system. Each

output buffer limits EMI by keeping the rise/fall time above 1 ns. Slow rise/fall times can induce additive phase

noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall time

below 5 ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage level

of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions. Each

output is active low when not requested to avoid false clocking of the load device.

LDO

A low noise 1.8-V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally

available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock

source for optimum phase noise performance. The input range of the LDO allows the device to be powered

directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,

the device enters a low power shutdown mode consuming less than 1

μA from the battery. The LDO requires an

output decoupling capacitor in the range of 1

μF to 10 μF for compensation and high frequency PSR. This

capacitor must stay within the specified range over the entire operating temperature range. An input bypass

capacitor of 1

μF or larger is recommended.

10

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): CDC3RL02