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LM3263TMX/NOPB 데이터시트(PDF) 21 Page - Texas Instruments

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부품명 LM3263TMX/NOPB
상세설명  LM3263 High-Current Step-Down DC-DC Converter with MIPI짰 RF Front-End Control Interface for RF Power Amplifiers
PDF  39 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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LM3263TMX/NOPB 데이터시트(HTML) 21 Page - Texas Instruments

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LM3263
www.ti.com
SNVS837 – JUNE 2013
PROGRAMMABLE REGISTERS
Addr
Register Contents
00h
REGISTER _0
Bits
Function
Default
Trigger*
R/W
Description
7
RSVD
0
N/A
N/A
Reserved
Register 00h interacts with Register 03h.
DC-DC converter mode and output voltage control bits
00h : Low-Power Mode
01h : Reserved
02h : Standby Mode
03h to 7Eh : Active Mode, Setting Output Voltage is
6:0
VSET[7:1]
00h
Yes
R/W
enabled. Output voltage can be set 0.4V to 3.6V by
0Dh to 78h with 30 mV steps
7Fh : Forced-Bypass Mode
VSET[7:1] (dec) = Desired VOUT / 0.03 (round up
decimals), then converts a decimal number to
hexadecimal.
01h
SMPS_CFG
Bits
Function
Default
Trigger*
R/W
Description
7:6
RSVD
0
N/A
N/A
Reserved
Switching mode select bit
5
MODE
0
Yes
R/W
0: Forced PWM Mode (PWM only)
1: Auto-PFM Mode (PFM/PWM)
Forced bypass bit
4
BYPS
0
Yes
R/W
0: Auto-Bypass Mode
1: Forced-Bypass Mode
3:0
RSVD
0h
N/A
N/A
Reserved
02h
GPO_CTRL
Bits
Function
Default
Trigger*
R/W
Description
GPO1 output control
7
GPO1_OUT
0
Yes
R/W
0: Low state
1: High state
GPO1 Mode Selection
6
GPO1_MODE
0
Yes
R/W
0 : General Purpose Output disabled
1 : General Purpose output driven by GPO1_OUT.
5:0
RSVD
00h
N/A
N/A
Reserved
03h
VSET_CTRL
Bits
Function
Default
Trigger*
R/W
Description
DC-DC converter mode and output voltage fine control
bits
00h-01h : Low-Power Mode
02h-03h : Reserved
04h-05h : Standby Mode
06h to FDh : Active Mode, Setting Output Voltage is
7:0
VSET[7:0]
00h
Yes
R/W
enabled. Output voltage can be set 0.4V to 3.6V by
1Bh to F0h with 15 mV steps
FEh-FFh : Forced Bypass Mode.
VSET[7:0] (dec) = Desired VOUT / 0.015 (round up
decimals), then converts a decimal number to
hexadecimal.
1Ah
RFFE_STATUS
Bits
Function
Default
Trigger*
R/W
Description
7
Software Reset. A write to '1' will cause all registers
SWRESET
0
No
except for USID to be reset. Will always read back '0'.
6
Set if parity error detected in command frame. Cleared
CMD_FRAME_PERR
0
No
on read. Write will have no effect on this bit.
5
Error when transaction interrupted by new SSC.
CMD_LENGTH_ERR
0
No
Cleared on read. Write will have no effect on this bit.
4
RSVD
0
No
Reserved
Copyright © 2013, Texas Instruments Incorporated
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