SPEAR320-2 datasheet(32/73 Pages) STMICROELECTRONICS

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Pin description

SPEAr320

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Doc ID 16755 Rev 5

4.3

Shared I/O pins (PL_GPIOs)

The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics:

–

Output buffer: TTL 3.3 V capable up to 10 mA

–

Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)

The PL_GPIOs can be configured in different modes. This allows SPEAr320 to be tailored

for use in various applications like:

–

Metering concentrators

–

Large power supply controllers

–

Small printers

4.3.1

PL_GPIO pin description

4.3.2

Configuration modes

This section describes the main operating modes created by using a selection of the

embedded IPs.

The following modes can be selected by programming some control registers present in the

reconfigurable array subsystem.

●

Mode 1: SMII automation networking mode

●

Mode 2: MII automation networking mode

●

Mode 3: Expanded automation mode

●

Mode 4: Printer mode

Table 11: PL_GPIO multiplexing scheme shows all the I/O functions available in each mode.

Mode 1 is the default mode for SPEAr320.

Table 10.

PL_GPIO pin description

Group

Signal name

Ball

Direction

Function

Pin type

PL_GPIOs

PL_GPIO_97...

PL_GPIO_0

(see the

Table 11)

I/O

General

purpose I/O or

multiplexed pins

(see Table 11)

(see the

introduction of

the Section 4.3

here above)

PL_CLK1...

PL_CLK4

programmable

logic external

clocks

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