ZPSD301B-70J datasheet(15/85 Pages) STMICROELECTRONICS

15 / 85 page

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PSD3XX Family

Multiplexed Address/Data

Non-Multiplexed Address/Data

8-bit Data Bus

I/O or low-order address

Port A

lines or Low-order multiplexed

D0–D7 data bus byte

address/data byte

Port B

I/O and/or CS0–CS7

AD0/A0–AD7/A7

Low-order multiplexed

address/data byte

Low-order address bus byte

AD8/A8–AD15/A15

High-order address

High-order address bus byte

bus byte

16-bit Data Bus

I/O or low-order address

Port A

lines or low-order multiplexed

Low-order data bus byte

address/data byte

Port B

I/O and/or CS0–CS7

High-order data bus byte

AD0/A0–AD7/A7

Low-order multiplexed

address/data byte

Low-order address bus byte

AD8/A8–AD15/A15

High-order multiplexed

address/data byte

High-order address bus byte

8.0

Operating

Modes (MCU

Configurations)

(cont.)

Table 3. Bus and Port Configuration Options

9.0

Programmable

Address

Decoder (PAD)

The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B

(Figure 4). PAD A is used to generate chip select signals derived from the input address to

the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals.

PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the

decoding to select external devices or as a random logic replacement.

PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft

based on the designer’s input. The PAD’s non-volatile configuration is stored in a

re-programmable CMOS EPROM. Windowed packages are available for erasure by the

user. See Table 4 for a list of PAD A and PAD B functions.

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