ICS810001DK-21 REVISION B APRIL 13, 2010

13

©2010 Integrated Device Technology, Inc.

ICS810001-21 Data Sheet

FEMTOCLOCK™ DUAL VCXO VIDEO PLL

Schematic Example

Figure 3 shows an example of the ICS810001-21 application

close as possible to the power pin. The input is driven by a 3.3V 17

Ω

LVCMOS driver. An optional 3-pole filter can also be used for

additional spur reduction. It is recommended that the loop filter

components be laid out for the 3-pole option. This will also allow the

2-pole filter to be used. For the LVCMOS output, a termination

example is shown in this schematic. For more termination

approaches, please refer to the LVCMOS Termination Application

Note.

Figure 3. ICS810001-21 Schematic Example

U1

810001-21 Schematic

LF1

1

LF0

2

ISET

3

VDD

4

nBP0

5

GND

6

CLK_SEL

7

CLK1

8

VDDA

17

VDDO

18

Q

19

GND

20

OE

21

nBP1

22

N1

23

N0

24

12pF

12pF

C8

.01uF

X1

VDD

Set Logic

Input to '0'

To Logic

Input

pins

Logic Control Input Examples

To Logic

Input

pins

Set Logic

Input to '1'

RU2

Not Install

RU1

1K

RD2

1K

RD1

Not Install

VDD

VDD

MR Control

VDDA

X2

Pin25

R6

TBD

Cp2

TBD

Cp1

TBD

Rs1

TBD

Cs1

TBD

LF1

3-pole loop filter example -

(optional)

LF0

VDD

Q1

Driv er_LVCMOS

Q2

Driv er_LVCMOS

Rs

150K

R1

33

R2

33

Pin18

Pin11

Pin4

Rset 2.21K

TL2

Zo = 50

TL1

Zo = 50

C5

.01uF

VDD

2-pole loop filter

C10

.01uF

C9

10uF

R3

10

VDD

C1spare

C2spare

C3 spare

C4 spare

Cs

.22uF

Cp

.001uF

C6

.01uF

VDDX

C12

.01uF

C11

10uF

R4

10

C7

.01uF

VDD

VDDX

VDD

VDDA

VDD

R5

33

TL3

Zo = 50

Receiv er