REV. B

DAC08

–5–

DAC08N

DAC08G

DAC08GR

Parameter

Symbol

Conditions

Limit

Limit

Limit

Unit

Resolution

8

8

8

Bits min

Monotonicity

8

8

8

Bits min

Nonlinearity

NL

±0.1

±0.19

±0.39

% FS max

Output Voltage

Full-Scale Current

+18

+18

+18

V max

Compliance

Change < 1/2 LSB

–10

–10

–10

V min

Full-Scale Current

2.04

2.04

2.04

mA max

Ω

1.94

1.94

1.94

mA min

Full-Scale Symmetry

±8

±8

±16

µA max

Zero-Scale Current

24

4

µA max

Output Current Range

V– = –10 V,

2.1

2.1

2.1

mA min

V– = –12 V,

4.2

4.2

4.2

mA min

Ω

Logic Input “0”

0.8

0.8

0.8

V max

Logic Input “1”

22

2

V min

Logic Input Current

Logic “0”

±10

±10

±10

µA max

Logic “1”

±10

±10

±10

µA max

Logic Input Swing

V– = –15 V

+18

+18

+18

V max

–10

–10

–10

V min

Reference Bias Current

–3

–3

–3

µA max

Power Supply

V+ = +4.5 V to +18 V

0.01

0.01

0.01

% FS/% V max

Sensitivity

V– = –4.5 V to –18 V

Power Supply Current

I+

±15 V

3.8

3.8

3.8

mA max

≤ 2.0 mA

–7.8

–7.8

–7.8

µA max

Power Dissipation

±15 V

174

174

174

mW max

≤ 2.0 mA

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

WAFER TEST LIMITS