JS28F512P30TFA datasheet(18/86 Pages) MICRON

18 / 86 page

P30-65nm

Datasheet

Sept 2012

Order Number: 208042-0

5.5

Output Disable

When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-

impedance (High-Z) state; WAIT is also placed in High-Z.

5.6

Standby

When CE# is deasserted the device is deselected and placed in standby, substantially

reducing power consumption. In standby, the data outputs are placed in High-Z,

independent of the level placed on OE#. Standby current, ICCS, is the average current

measured over any 5ms time interval, 5μs after CE# is deasserted. During standby,

average current is measured over the same time interval 5μs after CE# is deasserted.

When the device is deselected (while CE# is deasserted) during a program or erase

operation, it continues to consume active power until the program or erase operation is

completed.

5.7

Reset

As with any automated device, it is important to assert RST# when the system is reset.

When the system comes out of reset, the system processor attempts to read from the

flash memory if it is the system boot device. If a CPU reset occurs with no flash

memory reset, improper CPU initialization may occur because the flash memory may

be providing status information rather than array data. Flash memory devices from

Numonyx allow proper CPU initialization following a system reset through the use of the

RST# input.

After initial power-up or reset, the device defaults to asynchronous Read Array mode,

and the Status Register is set to 0x80.

When RST# is driven low (RST# asserted), the flash device enters reset mode. Then all

internal circuits are de-energized, and the output drivers are placed in High-Z. If RST#

is asserted during a program or erase operation, the operation is terminated and the

memory contents at the aborted location (for a program) or block (for an erase) are no

longer valid. A device reset also clears the Status Register. See Table 18, “Power and

Reset” on page 44 for RST# timing detail.

When RST# is driven high (RST# deasserted), a minimum wait is required before the

flash device is able to perform normal operations. Please consider tPHQV (R5) and tPHWL

(W1) during system design. see Table 25, “AC Read Specifications -” on page 51. and

Section 26, “AC Write Specifications” on page 55. After this wake-up interval passes,

normal operation is ready for execution.

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