LIS3DSHTR datasheet(38/53 Pages) STMICROELECTRONICS

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LIS3DSH

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Doc ID 022405 Rev 1

8.18

VFC_1 (1Bh)

Vector coefficient register 1 for DIff filter.

8.19

VFC_2 (1Ch)

Vector coefficient register 2 for DIff filter.

8.20

VFC_3 (1Dh)

Vector coefficient register 3 for FSM2 filter.

8.21

VFC_4 (1Eh)

Vector coefficient register 4 for DIff filter.

Table 43.

STAT register description

LONG

0=no interrupt, 1=long counter (LC) interrupt flag common for both SM

SYNCW

Synchronization for external Host Controller interrupt based on output data

0=no action waiting from host; 1=action from host based on output data

SYNC1

0=SM1 running normally, 1=SM1 stopped and await restart request from SM2

SYNC2

0=SM2 running normally, 1=SM2 stopped and await restart request from SM1

INT_SM1

SM1 - Interrupt Selection - 1=SM1 interrupt enable; 0: SM1 interrupt disable

NT_SM2

SM2 - Interrupt Selection - 1=SM2 interrupt enable; 0: SM2 interrupt disable

DOR

Data overrun indicates not read data from output register when next data samples

measure start; 0=no overrun, 1=data overrun data overrun bit is reset when next

sample is ready

DRDY

data ready from output register

0=data not ready, 1=data ready

Table 44.

Vector filter coefficient register 1 default value

000

Table 45.

Vector filter coefficient register 2 default value

000

Table 46.

Vector filter coefficient register 3 default value

000

Table 47.

Vector filter coefficient register 4 default value

000

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