Data Sheet

AD8436

Rev. B | Page 19 of 24

Figure 47. Photograph of the AD8436-EVALZ

TSUM

TACIN

VCC

VEE

GND5

GND4

GND3

GND2

DC

OUT

TIBUFOUT

TIBFIN+

VEE

CAVG

VCC

OBUFOUT

IGND

OBUFIN+

OBUFIN–

OBUFV+

OUT

DNC

IBUFIN–

IBUFOUT

IBUFIN+

SUM

IBUFV+

1

4

3

2

5

8

7

6

9

12

11

10

16

15

14

13

TCAVG

CORE

BUF

CORE

BUF

TOBFOUT

GND1

+

TDCOUT

GND6

SDCOUT

CIN

10µF

DC

AC

TRMSIN

TIBFIN–

TOGND

TOUT

TIGND

TOBUFIN+

TOBUFIN−

TOBUFV+

TIBUFV+

EN

EN

DIS

IBUF_VCC

DIS

TBUFGN

OGND

BUF

GAIN

CCF

+

VEE

+

19

18

17

20

INCOUP

DNC

RMS

TCCF

AD8436

+

10µF

50V

–40°C TO +125°C

2.2µF

1.5µF

0.1µF

CAVG

10µF

CCF

0.1µF

X8R

C4

0.1µF

CLPF

3.3µF

C5

0.47µF

8.06kΩ

0Ω

R8

0Ω

0Ω

0Ω

R2

0Ω

0Ω

R1

10MΩ

DNI

0Ω

C2

10µF

50V

–40°C TO

+125°C

(GRN)

+V

(RED)

OBUF_VCC

CORE_BUF

AC_IN

3

FOR SINGLE SUPPLY OPERATION, REMOVE R6, SHORT OR REPLACE C3 WITH A 0Ω RESISTOR AND CONNECT THE SUPPLY GROUND OR RETURN TO

THE GREEN TEST LOOP –V.

4

TO CONFIGURE THE FET INPUT BUFFER FOR GAIN OF 2, INSTALL 0Ω RESISTOR AT R5 AND REMOVE RFBH.

Figure 48. Evaluation Board Schematic