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ADP150AUJZ-2.8-R7 데이터시트(PDF) 18 Page - Analog Devices

부품명 ADP150AUJZ-2.8-R7
상세설명  Ultralow Noise, 150 mA CMOS Linear Regulator
PDF  20 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADP150AUJZ-2.8-R7 데이터시트(HTML) 18 Page - Analog Devices

Back Button ADP150AUJZ-2.8-R7 Datasheet HTML 12Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 13Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 14Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 15Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 16Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 17Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 18Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 19Page - Analog Devices ADP150AUJZ-2.8-R7 Datasheet HTML 20Page - Analog Devices  
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ADP150
Data Sheet
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*1.00 MAX
*0.90 MAX
0.70 MIN
2.90 BSC
54
12
3
SEATING
PLANE
Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.800
0.760 SQ
0.720
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
1
2
B
BALL A1
IDENTIFIER
0.40
REF
0.660
0.600
0.540
END VIEW
0.280
0.260
0.240
0.430
0.400
0.370
SEATING
PLANE
0.230
0.200
0.170
COPLANARITY
0.05
Figure 50.4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-3)
Dimensions show in millimeters



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