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AD9914PCBZ 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD9914PCBZ
상세설명  3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
PDF  48 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9914PCBZ 데이터시트(HTML) 6 Page - Analog Devices

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AD9914
Data Sheet
Rev. C | Page 6 of 48
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PARALLEL PORT TIMING
Write Timing
Address Setup Time to
WR Active
1
ns
Address Hold Time to
WR Inactive
0
ns
Data Setup Time to
WR Inactive
3.8
ns
Data Hold Time to
WR Inactive
0
ns
WR Minimum Low Time
2.1
ns
WR Minimum High Time
3.8
ns
Minimum
WR Time
10.5
ns
Read Timing
Address to Data Valid
92
ns
Address Hold to
RD Inactive
0
ns
RD Active to Data Valid
69
ns
RD Inactive to Data Tristate
50
ns
RD Minimum Low Time
69
ns
RD Minimum High Time
50
ns
SERIAL PORT TIMING
SCLK Clock Rate (1/tCLK )
80
MHz
SCLK duty cycle = 50%
SCLK Pulse Width High, tHIGH
1.5
ns
SCLK Pulse Width Low, tLOW
5.1
ns
SDIO to SCLK Setup Time, tDS
4.9
ns
SDIO to SCLK Hold Time, tDH
0
ns
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
78
ns
CS to SCLK Setup Time, tS
4
ns
CS to SCLK Hold Time, tH
0
ns
CS Minimum Pulse Width High, tPWH
4
ns
DATA PORT TIMING
D[31:0] Setup Time to SYNC_CLK
2
ns
D[31:0] Hold Time to SYNC_CLK
0
ns
F[3:0] Setup Time to SYNC_CLK
2
ns
F[3:0] Hold Time to SYNC_CLK
0
ns
IO_UPDATE Pin Setup Time to
SYNC_CLK
2
ns
IO_UPDATE Pin Hold Time to
SYNC_CLK
0
ns
Profile Pin Setup Time to SYNC_CLK
2
ns
Profile Pin Hold Time to SYNC_CLK
0
ns
DR_CTL/DR_HOLD Setup Time to
SYNC_CLK
2
ns
DR_CTL/DR_HOLD Hold Time to
SYNC_CLK
0
ns



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