AD5304ARMZ datasheet(5/24 Pages) AD

부품명	AD5304ARMZ

상세설명	2.5 V to 5.5 V, 500 關A, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages

PDF	24 Pages

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Data Sheet

AD5304/AD5314/AD5324

Rev. H | Page 5 of 24

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2, 3

Limit at TMIN, TMAX

VDD = 2.5 V to 3.6 V

VDD = 3.6 V to 5.5 V

Unit

Test Conditions/Comments

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

4.5

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

1 Guaranteed by design and characterization, not production tested.

2 All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2.

3 See Figure 2.

SCLK

DIN

DB15

DB0

SYNC

Figure 2. Serial Interface Timing Diagram

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