| 전자부품 데이터시트 검색엔진 |
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DSPIC33FJ32GS406 데이터시트(PDF) 21 Page - Microchip Technology |
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DSPIC33FJ32GS406 데이터시트(HTML) 21 Page - Microchip Technology |
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21 / 456 page ![]() 2009-2012 Microchip Technology Inc. DS70591E-page 21 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FLT1-FLT23 SYNCI1-SYNCI4 SYNCO1-SYNCO2 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H PWM5L PWM5H PWM6L PWM6H PWM7L PWM7H PWM8L PWM8H PWM9L PWM9H I I O O O O O O O O O O O O O O O O O O O ST ST — — — — — — — — — — — — — — — — — — — Fault inputs to PWM module. External synchronization signal to PWM master time base. PWM master time base for external device synchronization. PWM1 low output. PWM1 high output. PWM2 low output. PWM2 high output. PWM3 low output. PWM3 high output. PWM4 low output. PWM4 high output. PWM5 low output. PWM5 high output. PWM6 low output. PWM6 high output. PWM7 low output. PWM7 high output. PWM8 low output. PWM8 high output. PWM9 low output. PWM9 high output. PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST Data I/O pin for Programming/Debugging Communication Channel 1. Clock input pin for Programming/Debugging Communication Channel 1. Data I/O pin for Programming/Debugging Communication Channel 2. Clock input pin for Programming/Debugging Communication Channel 2. Data I/O pin for Programming/Debugging Communication Channel 3. Clock input pin for Programming/Debugging Communication Channel 3. MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P Positive supply for analog modules. AVSS P P Ground reference for analog modules. VDD P — Positive supply for peripheral logic and I/O pins. VCAP P — CPU logic filter capacitor connection. VSS P — Ground reference for logic and I/O pins. TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Type Buffer Type Description Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic |
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