 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
DAC8512FSZ 데이터시트(PDF) 2 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
DAC8512FSZ 데이터시트(HTML) 2 Page - Analog Devices |
|
|
2 / 20 page  REV. A –2– DAC8512–SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 2 12 Bits Relative Accuracy INL E Grade –1 ±1/4 +1 LSB F Grade –2 ±3/4 +2 LSB Differential Nonlinearity DNL No Missing Codes –1 ±3/4 +1 LSB Zero-Scale Error VZSE Data = 000H +1/2 +3 LSB Full-Scale Voltage VFS Data = FFFH 3 E Grade 4.087 4.095 4.103 V F Grade 4.079 4.095 4.111 V Full-Scale Tempco TCVFS Notes 3, 4 16 ppm/ °C ANALOG OUTPUT Output Current IOUT Data = 800H ±5 ±7mA Load Regulation at Full Scale LREG RL = 402 Ω to ∞, Data = 800H 1 3 LSB Capacitive Load CL No Oscillation 4 500 pF LOGIC INPUTS Logic Input Low Voltage VIL 0.8 V Logic Input High Voltage VIH 2.4 V Input Leakage Current IIL 10 µA Input Capacitance CIL 10 pF INTERFACE TIMING SPECIFICATIONS 1, 4 Clock Width High tCH 30 10 ns Clock Width Low tCL 30 10 ns Load Pulse Width tLDW 20 ns Data Setup tDS 15 10 ns Data Hold tDH 15 5 ns Clear Pulse Width tCLRW 30 20 ns Load Setup tLD1 15 ns Load Hold tLD2 10 ns Select tCSS 30 ns Deselect tCSH 20 ns AC CHARACTERISTICS 4 Voltage Output Settling Time tS To ±1 LSB of Final Value5 16 µs DAC Glitch 15 nV s Digital Feedthrough 15 nV s SUPPLY CHARACTERISTICS Positive Supply Current IDD VIH = 2.4 V, VIL = 0.8 V, No Load 1.5 2.5 mA VDD = 5 V, VIL = 0 V, No Load 0.5 1 mA Power Dissipation PDISS VIH = 2.4 V, VIL = 0.8 V, No Load 7.5 12.5 mW VDD = 5 V, VIL = 0 V, No Load 2.5 5 mW Power Supply Sensitivity PSS ∆V DD = ±5% 0.002 0.004 %/% NOTES 1All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 21 LSB = 1 mV for 0 V to +4.095 V output range. 3Includes internal voltage reference error. 4These parameters are guaranteed by design and not subject to production testing. 5The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. (@ VDD = +5.0 V 5%, –40 C ≤ T A ≤ +85 C, unless otherwise noted) |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
