DS1683

Total-Elapsed-Time and Event Recorder with Alarm

13

Maxim Integrated

REGISTERS 0Ah–0Dh: ETC REGISTER

REGISTERS 10h–11h: EVENT COUNTER ALARM LIMIT REGISTER

Factory Default

00 00 00 00h

Read Access

All

Write Access

PW

Memory Type

Shadowed EEPROM, Nonvolatile

Memory

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0Ah

0Bh

0Ch

0Dh

BIT 7

BIT 0

The ETC register is a shadowed EEPROM register that contains the accumulated time in 250ms increments that the EVENT pin

from the shadowed EEPROM location is loaded into the ETC counter memory (SRAM). When the EVENT pin is high, it is this

SRAM memory that is incremented once every 250ms. On the falling edge of the EVENT pin, this value in SRAM memory is then

written to the shadowed EEPROM memory to store the accumulated time in 250ms increments.

Factory Default

00 00h

Read Access

All

Write Access

PW

Memory Type

Shadowed EEPROM, Nonvolatile

Memory

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

10h

11h

BIT 7

BIT 0

The Event Counter Alarm Limit is a shadowed EEPROM register, and when the Event Counter register value equals or exceeds

the Event Counter Alarm Limit value, the EVENT flag bit (EVENT AF bit, Register 01h, bit 1) goes active high. When the Event

Counter register value drops below the Event Counter Alarm Limit value, the EVENT AF bit automatically clears.