STM8AF52AA datasheet(71/110 Pages) STMICROELECTRONICS

71 / 110 page

STM8AF52/62xx, STM8AF51/61xx

Electrical characteristics

Doc ID 14395 Rev 9

71/110

10.3.6

I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All

unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 40.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Low-level input voltage

—

-0.3 V

0.3 x VDD

—

VIH

High-level input voltage

0.7 x VDD

VDD + 0.3 V

Vhys

Hysteresis(1)

—

0.1 x

VDD

—

VOH

High-level output voltage

Standard I/0, VDD = 5 V,

I = 3 mA

VDD - 0.5 V

—

Standard I/0, VDD = 3 V,

I = 1.5 mA

VDD - 0.4 V

—

VOL

Low-level output voltage

High sink and true open

drain I/0, VDD = 5 V

I = 8 mA

——

0.5

Standard I/0, VDD = 5 V

I = 3 mA

——

0.6

Standard I/0, VDD = 3 V

I = 1.5 mA

——

0.4

Rpu

Pull-up resistor

VDD = 5 V, VIN = VSS

tR, tF

Rise and fall time

(10% - 90%)

Fast I/Os

Load = 50 pF

——

35(2)

Standard and high sink I/Os

Load = 50 pF

—

125(2)

Fast I/Os

Load = 20 pF

20(2)

Standard and high sink I/Os

Load = 20 pF

50(2)

Ilkg

Digital input pad leakage

current

VSS ≤ VIN ≤ VDD

——

±1

µA

Ilkg ana

Analog input pad leakage

current

VSS ≤ VIN ≤ VDD

-40 °C < TA < 125 °C

—

±250

VSS ≤ VIN ≤ VDD

-40 °C < TA < 150 °C

—

±500

Ilkg(inj)

Leakage current in

adjacent I/O(3)

Injection current ±4 mA

—

±1(3)

µA

IDDIO

Total current on either

VDDIO or VSSIO

Including injection currents

—

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

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