STM8AF528A datasheet(78/110 Pages) STMICROELECTRONICS

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Electrical characteristics

STM8AF52/62xx, STM8AF51/61xx

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Doc ID 14395 Rev 9

10.3.9

SPI interface

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under ambient temperature, fMASTER frequency, and VDD supply voltage

conditions. tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 43.

SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

VDD < 4.5 V

6(1)

VDD = 4.5 V to 5.5 V

8(1)

tr(SCK)

tf(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

—

25(2)

tsu(NSS)

(3)

NSS setup time

Slave mode

4 * tMASTER

—

th(NSS)

(3)

NSS hold time

Slave mode

—

tw(SCKH)

(3)

tw(SCKL)

(3)

SCK high and low time

Master mode

tSCK/2 - 15

tSCK/2 + 15

tw(SCKH)

(3)

tw(SCKL)

(3)

tsu(MI)

(3)

tsu(SI)

(3)

Data input setup time

Master mode

—

Slave mode

—

th(MI)

(3)

th(SI)

(3)

Data input hold time

Master mode

—

Slave mode

—

ta(SO)

(3)(4)

Data output access time

Slave mode

—

3* tMASTER

tdis(SO)

(3)(5) Data output disable time

Slave mode

tv(SO)

(3)

Data output valid time

Slave mode

(after enable edge)

VDD < 4.5 V

—

VDD = 4.5 V to 5.5 V

—

tv(MO)

(3)

Data output valid time

Master mode (after enable edge)

—

th(SO)

(3)

Data output hold time

Slave mode (after enable edge)

—

th(MO)

(3)

Master mode (after enable edge)

—

fSCK < fMASTER/2.

The pad has to be configured accordingly (fast mode).

Values based on design simulation and/or characterization results, and not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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