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MCR03EZPFX1002 데이터시트(PDF) 18 Page - International Rectifier

부품명 MCR03EZPFX1002
상세설명  HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
PDF  36 Pages
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제조업체  IRF [International Rectifier]
홈페이지  http://www.irf.com
Logo IRF - International Rectifier

MCR03EZPFX1002 데이터시트(HTML) 18 Page - International Rectifier

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18
IR3837MPbF
Rev 1.31
TIMING DIAGRAM OF PGOOD FUNCTIONS
Fig.11 Non-sequence Startup and Vref Margin (Vp =Vcc)
Table 2. The required conditions to achieve simultaneous / ratiometric tracking and sequencing
operations with the circuit configuration of Fig. 8
R
E/RF >RC/RD
Ramp up from 0V
> 1.5V
Ratiometric Tracking
R
E/RF =RC/RD
Ramp up from 0V
> 1.5V
Simultaneous Tracking
R
A/RB >RE/RF > RC/RD
Ramp up from 0V
0.6V
Ratiometric Sequencing
R
A/RB > RE/RF =RC/RD
Ramp up from 0V
0.6V
Simultaneous Sequencing
-
> 1.5V
0.6V (Float)
Normal (Non-Sequencing,
Non-Tracking)
Required Condition
Vp
Vref (slave)
Operating Mode
R
E/RF >RC/RD
Ramp up from 0V
> 1.5V
Ratiometric Tracking
R
E/RF =RC/RD
Ramp up from 0V
> 1.5V
Simultaneous Tracking
R
A/RB >RE/RF > RC/RD
Ramp up from 0V
0.6V
Ratiometric Sequencing
R
A/RB > RE/RF =RC/RD
Ramp up from 0V
0.6V
Simultaneous Sequencing
-
> 1.5V
0.6V (Float)
Normal (Non-Sequencing,
Non-Tracking)
Required Condition
Vp
Vref (slave)
Operating Mode
Internal SS
0
0
0
0
Vref
PGood
256/Fs
Fb
0.7V
1.3V
2.0V
SSOK
256/Fs
0.6V
1.15*Vref
0.85*Vref
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage is
compared to a threshold. The threshold is set
differently at different operating modes and the
results of the comparison sets the PGood signal.
Figures 11, 12, and 13 show the timing diagram
of the PGood signal at different operating modes.
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation.



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