EP2C8 datasheet(30/36 Pages) ALTERA

부품명	EP2C8

상세설명	Enhanced Configuration (EPC) Devices Datasheet

PDF	36 Pages

Scroll/Zoom	100%

제조업체	ALTERA [Altera Corporation]

홈페이지	http://www.altera.com

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30 / 36 page

Page 30

Timing Information

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

tECLK

EXCLK

input period

—

tECLKH

EXCLK

input duty cycle high time

40% duty cycle

—

tECLKL

EXCLK

input duty cycle low time

40% duty cycle

—

tECLKR

EXCLK

input rise time

100 MHz

—

tECLKF

EXCLK

input fall time

100 MHz

—

tPOR (4)

POR time

2 ms

100 ms

100

120

Notes to Table 14:

(1) To calculate tOH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns.

(2) This parameter is used for CRC error detection by the FPGA.

(3) This parameter is used for CONF_DONE error detection by the EPC device.

(4) The FPGA VCCINT ramp time should be less than 1 ms for 2-ms POR and it should be less than 70 ms for 100-ms POR.

Table 14. EPC Device Configuration Parameters (Part 2 of 2)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

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