SL40307A-R19KHF datasheet(19/53 Pages) IRF

19 / 53 page

IR3846

19 www.irf.com

August 01, 2013

Vcc

PVin=Vin

Intl_SS

> 1.2V

> 1.0V

Figure 5: Recommended startup for Normal operation

Vcc

PVin=Vin

Intl_SS

> 1.2V

Figure 6: Recommended startup for sequencing

operation (ratiometric or simultaneous)

Vcc

PVin=Vin

VDDQ

Vref

> 1.2V

VDDQ/2

VTT Tracking

Figure 7: Recommended startup for memory tracking

operation (Vtt-DDR)

Figure 5 shows the recommended startup sequence

for

the

normal

(non-tracking,

non-sequencing)

operation of IR3846, when Enable is used as a logic

input. In this operating mode Vref is left floating.

Figure 6 shows the recommended startup sequence

for sequenced operation of IR3846 with Enable used

as logic input. Figure 7 shows the recommended

startup sequence for tracking operation of IR3846 with

Enable used as logic input. For this mode of

operation, Vref should be connected to LGND.

PRE-BIAS STARTUP

IR3846 is able to start up into pre-charged output,

which prevents oscillation and disturbances of the

output voltage.

The output starts in asynchronous fashion and keeps

the synchronous MOSFET (Sync FET) off until the

first gate signal for control MOSFET (Ctrl FET) is

generated. Figure 8 shows a typical Pre-Bias

condition at start up. The sync FET always starts with

a narrow pulse width (12.5% of a switching period)

and gradually increases its duty cycle with a step of

12.5% until it reaches the steady state value. The

number of these startup pulses for each step is 16

and it’s internally programmed. Figure 9 shows the

series of 16x8 startup pulses.

[V]

[Time]

Pre-Bias

Voltage

Figure 8: Pre-Bias startup

...

HDRv

...

End of

LDRv

12.5%

25%

87.5%

...

Figure 9: Pre-Bias startup pulses

SOFT-START

IR3846 has an internal digital soft-start to control the

output voltage rise and to limit the current surge at the

start-up. To ensure correct start-up, the soft-start

sequence initiates when the Enable and VCC rise

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