LP55231 datasheet(27/53 Pages) TI

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LP55231

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SNOSCR5 – MARCH 2013

Table 3. Control Register Map (continued)

Hex

Read/Writ

Default Value

Bit(s)

Bit Mnemonic and Description

Address

After Reset

[7]

0xxxxxxx

Engine 1 mapping information, D8 output

[6]

x0xxxxxx

Engine 1 mapping information, D7 output

[5]

xx0xxxxx

Engine 1 mapping information, D6 output

[4]

xxx0xxxx

Engine 1 mapping information, D5 output

ENG1 MAPPING LSB

[3]

xxxx0xxx

Engine 1 mapping information, D4 output

[2]

xxxxx0xx

Engine 1 mapping information, D3 output

[1]

xxxxxx0x

Engine 1 mapping information, D2 output

[0]

xxxxxxx0

Engine 1 mapping information, D1 output

ENG2 MAPPING MSB

[0]

xxxxxxx0

Engine 2 mapping information, D9 output

[7]

0xxxxxxx

Engine 2 mapping information, D8 output

[6]

x0xxxxxx

Engine 2 mapping information, D7 output

[5]

xx0xxxxx

Engine 2 mapping information, D6 output

[4]

xxx0xxxx

Engine 2 mapping information, D5 output

ENG2 MAPPING LSB

[3]

xxxx0xxx

Engine 2 mapping information, D4 output

[2]

xxxxx0xx

Engine 2 mapping information, D3 output

[1]

xxxxxx0x

Engine 2 mapping information, D2 output

[0]

xxxxxxx0

Engine 2 mapping information, D1 output

ENG3 MAPPING MSB

[0]

xxxxxxx0

Engine 3 mapping information, D9 output

[7]

0xxxxxxx

Engine 3 mapping information, D8 output

[6]

x0xxxxxx

Engine 3 mapping information, D7 output

[5]

xx0xxxxx

Engine 3 mapping information, D6 output

[4]

xxx0xxxx

Engine 3 mapping information, D5 output

ENG3 MAPPING LSB

[3]

xxxx0xxx

Engine 3 mapping information, D4 output

[2]

xxxxx0xx

Engine 3 mapping information, D3 output

[1]

xxxxxx0x

Engine 3 mapping information, D2 output

[0]

xxxxxxx0

Engine 3 mapping information, D1 output

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