4TPC150M datasheet(28/40 Pages) TI

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0.7V

TPS704xxPWP

(FixedOutputOption)

22 F

0.22 F

250kW

47 F

EN1

EN2

>2V

<0.7V

>2V

<0.7V

EN2

EN1

IN2

IN1

OUT2

SENSE2

PG2

RESET

SENSE1

OUT1

RESET

PG2

OUT2

OUT1

95%

EN2

EN1

OUT1

OUT2

PG2

PG1

RESET

NOTES:A.t :TimeatwhichV

isgreaterthanV

and

islogichigh.

B.Thetimingdiagramisnotdrawntoscale.

UVLO

120ms

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010

www.ti.com

Application condition: VIN1 and VIN2 are tied to the

same fixed input voltage greater than VUVLO. MR is

initially logic high but is eventually toggled.

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 are at logic low.

Since VIN1 is greater than VUVLO and MR is at logic

high, RESET is also at logic high. When EN2 is taken

to logic low, VOUT2 turns on. Later, when EN1 is taken

to logic low, VOUT1 turns on. When VOUT2 reaches

95% of its regulated output voltage, PG2 goes to

logic high. When VOUT1 reaches 95% of its regulated

output voltage, PG1 goes to logic high. When MR is

taken to logic low, RESET is taken low. When MR

returns to logic high, RESET returns to logic high

after a 120-ms delay.

Figure 39. Timing When MR is Toggled

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