LPC810M021FN8 datasheet(49/71 Pages) NXP

49 / 71 page

LPC81xM

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Product data sheet

Rev. 3 — 29 July 2013

49 of 71

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

12.6 SPI interfaces

The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode.

Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for

all digital pins except the open-drain pins PIO0_10 and PIO0_11.

[1]

Capacitance on pin SPIn_SCK CSCK < 5 pF.

[2]

Tcy(clk) = DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the

LPC800 User manual UM10601.

Table 17.

SPI dynamic characteristics

Tamb = 40 C to 105 C; 1.8 V <= VDD <= 3.6 V. Simulated parameters sampled at the 50 % level of

the rising or falling edge; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

SPI master[1]

Tcy(clk)

clock cycle time

[2]

tDS

data set-up time

tDH

data hold time

tv(Q)

data output valid time

CL = 10 pF

0.5

th(Q)

data output hold time

CL = 10 pF

0.5

SPI slave

Tcy(clk)

tDS

data set-up time

tDH

data hold time

tv(Q)

data output valid time

CL = 10 pF

th(Q)

data output hold time

CL = 10 pF

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