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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LTC1263CS8 데이터시트(PDF) 4 Page - Linear Technology |
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LTC1263CS8 데이터시트(HTML) 4 Page - Linear Technology |
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4 / 8 page  4 LTC1263 BLOCK DIAGRAM C1+ C1– C1 C2+ C2– C2 S4B S4A S3A S3C S1 R1 R2 R3 BANDGAP REFERENCE OSCILLATOR VCC VOUT CIN COUT SHDN GND CHARGE PUMP S4C S3D S3B LTC1263 • BD VBGAP S1 AND S2 SHOWN WITH SHDN PIN LOW. S3A, S3B, S3C, S3D, S4A, S4B AND S4C SHOWN CHARGING C1 AND C2 WITH OSCILLATOR OUTPUT LOW AND VDIV < VBGAP – VHYST. AT OSCILLATOR OUTPUT HIGH, S3A, S3B, S3C AND S3D OPEN WHILE S4A, S4B AND S4C CLOSE TO CHARGE VOUT. COMPARATOR HYSTERESIS IS ±VHYST S2 VDIV CLK TIMING DIAGRAMS 1.4V 1.4V VSHDN VOUT 5.1V 12V tON tOFF VOUT VCC VCC 0V LTC1263 • F01 Figure 1. Timing Diagram 1 2 3 4 8 7 6 5 SHDN GND VOUT VCC C1– C1+ C2– C2+ LTC1263 C1 = 0.47 µF C2 = 0.47 µF LTC1263 • F02 C3 = 10 µF C4 = 10 µF VCC 4.75V TO 5.5V VSHDN VOUT Figure 2. Timing Circuit |
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