AD9854ASVZ datasheet(20/52 Pages) AD

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AD9854

Rev. E | Page 20 of 52

000 (SINGLE TONE)

MODE

TW1

000 (DEFAULT)

MASTER RESET

I/O UD CLK

Figure 35. Default State to User-Defined Output Transition

As with all Analog Devices DDS devices, the value of the

frequency tuning word is determined by

FTW = (Desired Output Frequency × 2N)/SYSCLK

where:

N is the phase accumulator resolution (48 bits in this instance).

Desired Output Frequency is expressed in hertz.

FTW (frequency tuning word) is a decimal number.

After a decimal number has been calculated, it must be rounded

to an integer and then converted to binary format, that is, a

series of 48 binary-weighted 1s and 0s. The fundamental sine

wave DAC output frequency range is from dc to one-half SYSCLK.

Changes in frequency are phase continuous, meaning that the

first sampled phase value of the new frequency is referenced from

the time of the last sampled phase value of the previous frequency.

The I and Q DACs of the AD9854 are always 90° out of phase.

The 14-bit phase registers do not independently adjust the

phase of each DAC output. Instead, both DACs are affected

equally by a change in phase offset.

The single-tone mode allows the user to control the following

signal qualities:

•

Output frequency to 48-bit accuracy

•

Output amplitude to 12-bit accuracy

•

Fixed, user-defined amplitude control

•

Variable, programmable amplitude control

•

Automatic, programmable, single-pin-controlled

on/off output shaped keying

•

Output phase to 14-bit accuracy

These qualities can be changed or modulated via the 8-bit

parallel programming port at a 100 MHz parallel byte rate or at

a 10 MHz serial rate. Incorporating this attribute permits FM,

AM, PM, FSK, PSK, and ASK operation in single-tone mode.

Unramped FSK (Mode 001)

When the unramped FSK mode is selected, the output frequency of

the DDS is a function of the values loaded into Frequency Tuning

Word Register 1 and Frequency Tuning Word Register 2 and the

logic level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29

chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex to

Parallel Address 9 hex), and a logic high chooses F2 (Frequency

Tuning Word 2, Parallel Register Address A hex to Parallel

continuous and are internally coincident with the FSK data pin

(Pin 29); however, there is deterministic pipeline delay between

the FSK data signal and the DAC output. (Refer to the pipeline

delays in Table 1.)

The unramped FSK mode, shown in Figure 36, represents

traditional FSK, radio teletype (RTTY), or teletype (TTY)

transmission of digital data. FSK is a very reliable means of

digital communication; however, it makes inefficient use of

the bandwidth in the RF spectrum. Ramped FSK, shown in

Figure 37, is a method of conserving bandwidth.

Ramped FSK (Mode 010)

This mode is a method of FSK whereby changes from F1 to F2

are not instantaneous, but are accomplished in a frequency sweep

or ramped fashion (the ramped notation implies that the sweep

is linear). Although linear sweeping, or frequency ramping, is

easily and automatically accomplished, it is only one of many

schemes. Other frequency transition schemes can be

implemented by changing the ramp rate and ramp step size on

the fly in a piecewise fashion.

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