Micrel, Inc.

MIC5166

June 2012

2

M9999-060612-A

Ordering Information

Part Number

Output Voltage

Junction Temperature Range

(1)

Package

Lead Finish

MIC5166YML

½VDDQ

–40

°C to +125°C

10-Pin 3mm

Pb-Free

Note:

1.

MLF

Pin Configuration

10-Pin 3mm

Pin Description

Pin Number

Pin Name

Description

1

VREF

output is used to provide the reference voltage for the memory chip. Connect a 1.0µF capacitor to

ground at this pin. This pin can sink and source 10mA.

2

BIAS

BIAS Supply Voltage. The BIAS supply is the power MOSFET gate drive supply voltage and the

from the BIAS pin to PGND

must be placed next to the IC.

3

AGND

Analog Ground. Internal signal ground for all low-power circuits.

4

VDDQ

4.7µF capacitor to ground at this pin.

5

PG

Power Good. This is an open drain output that indicates when the output voltage is within ±10% of the

reference voltage. The PG flag is asserted typically with 65µs delay when the enable is set low or

when the output goes outside ±10% the window threshold.

6

SNS

Feedback. Input to the error amplifier.

7

EN

Enable. Logic level control of the output. Logic HIGH enables the MIC5166 and a logic LOW shuts

down the MIC5166. In the off state, supply current of the device is greatly reduced (typically 0.2µA).

The EN pin should not be left open.

8

PGND

Power Ground. Internal ground connection to the source of the internal, low-side drive, N-channel

MOSFET.

9

VTT

Power Output. This is the connection to the source of the internal high-side N-channel MOSFET and

drain of the low-side N-channel MOSFET. This is a high-frequency, high-power connection, therefore

two 10µF output capacitors must be placed as close to the IC as possible.

10

VIN

3.6V. An input capacitor between the VIN pin and the PGND is required as close to the chip as

possible.

EP

ePad

Exposed Pad. Must be connected to a GND plane for best thermal performance.