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S3F82NB 데이터시트(PDF) 7 Page - Zilog, Inc. |
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S3F82NB 데이터시트(HTML) 7 Page - Zilog, Inc. |
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7 / 361 page ![]() PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BLOCK DIAGRAM nRESET VDD Port I/O and Interrupt Control SAM88RC CPU 64 K-byte ROM 4,112 byte Register File XIN Basic Timer 8-Bit Timer/Counter0 Comparator SIO LCD Controller/ Driver VSS XOUT XTIN XTOUT Watchdog Timer T0CLK/AD1/P0.1 T0OUT/T0PWM/T0CAP/AD3/P0.3 8-Bit TimerA 8-Bit TimerB T1CLK/AD0/P0.0 T1OUT/T1PWM/T1CAP/AD2/P0.2 10-bit ADC AD0-AD7/P0.0-P0.7 CIN0/P6.0 CIN1/P6.1 CIN2/P6.2 SCK/INT7/P1.7 SO/INT6/P1.6 SI/INT5/P1.5 VLC0-VLC4 COM0-COM7 COM8-COM15/SEG0-SEG7 SEG56-SEG87/P3.0-P5.7 SEG8-SEG55 Port 0 P0.0/AD0/T1CLK P0.1/AD1/T0CLK P0.2/AD2/T1OUT/T1PWM/T1CAP P0.3/AD3/T0OUT/T0PWM/T0CAP P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 Port 1 P1.0/INT0/VREF P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4/BUZ P1.5/INT5/SI P1.6/INT6/SO P1.7/INT7/SCK P10.0-P10.7/SEG24-SEG31 Port 10 Port 2 P2.0-P2.7/SEG56-SEG63 Port 5 P5.0/SEG80 P5.1/SEG81 P5.2/SEG82 P5.3/SEG83 P5.4/SEG84/INT8 P5.5/SEG85/INT9 P5.6/SEG86/INT10 P5.7/SEG87/INT11 Port 4 P4.0-P4.7/SEG72-SEG79 TEST Main OSC. Sub OSC. Low Voltage Reset Watch Timer BUZ/INT4/P1.4 AVREF/INT0/P1.0 Port 3 P3.0-P3.7/SEG64-SEG71 Port 9 P9.0-P9.7/SEG32-SEG39 Port 8 P8.0-P8.7/SEG40-SEG47 Port 7 P7.0-P7.7/SEG48-SEG55 P6.0-P6.2/CIN1-CIN2 Port 6 Figure 1-1. Block Diagram 4 |
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