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AD1981BBSTZ 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD1981BBSTZ
상세설명  AC 97 SoundMAX Codec
PDF  32 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD1981BBSTZ 데이터시트(HTML) 6 Page - Analog Devices

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AD1981B
Rev. C | Page 6 of 32
Parameter
Symbol
Min
Typ
Max
Unit
BIT_CLK Low Pulse Width
tCLK_LOW
32.56
38
ns
SYNC Frequency
48.0
kHz
SYNC Period
tSYNC_PERIOD
20.8
ms
Setup to Falling Edge of BIT_CLK
tSETUP
5
2.5
ns
Hold from Falling Edge of BIT_CLK
tHOLD
5
ns
BIT_CLK Rise Time
tRISECLK
2
4
6
ns
BIT_CLK Fall Time
tFALLCLK
2
4
6
ns
SYNC Rise Time
tRISESYNC
2
4
6
ns
SYNC Fall Time
tFALLSYNC
2
4
6
ns
SDATA_IN Rise Time
tRISEDIN
2
4
6
ns
SDATA_IN Fall Time
tFALLDIN
2
4
6
ns
SDATA_OUT Rise Time
tRISEDOUT
2
4
6
ns
SDATA_OUT Fall Time
tFALLDOUT
2
4
6
ns
End of Slot 2 to BIT_CLK, SDATA_IN Low
tS2_PDOWN
0
1.0
ms
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
tSETUP2RST
15
ns
Rising Edge of RESET to High Z Delay
tOFF
25
ns
Propagation Delay
15
ns
RESET Rise Time
50
ns
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
15
ns
1 Guaranteed but not tested.
2 Output jitter is directly dependent on crystal input jitter.
3 Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.
RESET
BIT_CLK
SDATA_IN
tRST_LOW
tRST2CLK
tTRI2ACTV
tTRI2ACTV
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
SYNC
BIT_CLK
tSYNC_HIGH
tSYNC2CLK
Figure 3. Warm Reset Timing



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