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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADSP-21062LABZ-160 데이터시트(PDF) 32 Page - Analog Devices |
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ADSP-21062LABZ-160 데이터시트(HTML) 32 Page - Analog Devices |
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32 / 64 page  Rev. F | Page 32 of 64 | March 2008 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Asynchronous Read/Write—Host to ADSP-2106x Use these specifications for asynchronous host processor accesses of an ADSP-2106x, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-2106x, the host can drive the RD and WR pins to access the ADSP-2106x’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. Not required if and address are valid tHBGRCSV after goes low. For first access after asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before or goes low or by tHBGRCSV after goes low. This is easily accomplished by driving an upper address signal high when is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. Table 19. Read Cycle 5 V and 3.3 V Unit Parameter Min Max Timing Requirements tSADRDL Address Setup/CS Low Before RD Low1 0ns tHADRDH Address Hold/CS Hold Low After RD 0ns tWRWH RD/WR High Width 6 ns tDRDHRDY RD High Delay After REDY (O/D) Disable 0 ns tDRDHRDY RD High Delay After REDY (A/D) Disable 0 ns Switching Characteristics tSDATRDY Data Valid Before REDY Disable from Low 2 ns tDRDYRDL REDY (O/D) or (A/D) Low Delay After RD Low2 10 ns tRDYPRD REDY (O/D) or (A/D) Low Pulse Width for Read 45 + 21DT/16 ns tHDARWH Data Disable After RD High3 28 ns 1 Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. 2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max. 3 For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max. Table 20. Write Cycle 5 V and 3.3 V Unit Parameter Min Max Timing Requirements tSCSWRL CS Low Setup Before WR Low 0 ns tHCSWRH CS Low Hold After WR High 0 ns tSADWRH Address Setup Before WR High 5 ns tHADWRH Address Hold After WR High 2 ns tWWRL WR Low Width 7 ns tWRWH RD/WR High Width 6 ns tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable 0 ns tSDATWH Data Setup Before WR High 5 ns tHDATWH Data Hold After WR High 1 ns Switching Characteristics tDRDYWRL REDY (O/D) or (A/D) Low Delay After WR/CS Low 10 ns tRDYPWR REDY (O/D) or (A/D) Low Pulse Width for Write 15 + 7DT/16 ns tSRDYCK REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 ns |
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