전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

APDS-9130 데이터시트(PDF) 21 Page - AVAGO TECHNOLOGIES LIMITED

부품명 APDS-9130
상세설명  Digital Proximity Sensor
PDF  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AVAGO [AVAGO TECHNOLOGIES LIMITED]
홈페이지  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

APDS-9130 데이터시트(HTML) 21 Page - AVAGO TECHNOLOGIES LIMITED

Back Button APDS-9130 Datasheet HTML 17Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 18Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 19Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 20Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 21Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 22Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 23Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 24Page - AVAGO TECHNOLOGIES LIMITED APDS-9130 Datasheet HTML 25Page - AVAGO TECHNOLOGIES LIMITED Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 31 page
background image
21
Device ID Register (0x12)
The ID register provides the value for the part number. The ID register is a read-only register.
7
6
5
4
3
2
1
0
ID
Device ID
0x12
FIELD
BITS
DESCRIPTION
ID
7:0
Part number identification
0x39 = APDS-9130
Status Register (0x13)
The Status Register provides the internal status of the device. This register is read only.
7
6
5
4
3
2
1
0
STATUS
Reserved
PSAT
PINT
Reserved
Reserved
Reserved
PVALID
Reserved
0x13
FIELD
BITS
DESCRIPTION
Reserved
7
Reserved.
PSAT
6
Proximity Saturation. Indicates that the proximity measurement is saturated
PINT
5
Proximity Interrupt. Indicates that the device is asserting a proximity interrupt.
Reserved
4
Reserved.
Reserved
3:2
Reserved.
PVALID
1
PS Valid. Indicates that the PS has completed an integration cycle.
Reserved
0
Reserved.
Proximity DATA Register (0x18 − 0x19)
Proximity data is stored as a 16-bit value. To ensure the data is read correctly, a two byte read I2C transaction should be
used with auto increment protocol bits set in the command register. With this operation, when the lower byte register
is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The
upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower
and upper registers.
REGISTER
ADDRESS
BITS
DESCRIPTION
PDATAL
0x18
7:0
Proximity data low byte
PDATAH
0x19
7:0
Proximity data high byte



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com