PPC5604EEMLH datasheet(54/75 Pages) FREESCALE

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MPC5604E Microcontroller Data Sheet, Rev. 4

Electrical characteristics

Freescale Semiconductor

3.18.5

External interrupt timing (IRQ pin)

Figure 21. External interrupt timing

3.18.6

FlexCAN timing

3.18.7

LINFlex timing

Minimum design target for interface frequency is 2 MBit/s.

Table 30. External interrupt timing1

1 IRQ timing specified at f

SYS = 64 MHz and VDD_HV_IOx = 3.0 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00.

No.

Symbol

Parameter

Conditions

Min

Max Unit

1tIPWL

IRQ pulse width low

—

tCYC

2tIPWH

IRQ pulse width high

—

tCYC

3tICYC

IRQ edge to edge time2

2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

—4+N3

3 N = ISR time to clear the flag

—tCYC

Table 31. FlexCAN timing1

1 FlexCAN timing specified at f

SYS = 64 MHz, VDD = 1.35 V to 1.65 V, VDDEH = 3.0 V to 5.5 V, VRC33 and

VDDPLL = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00.

Num

Characteristic

Symbol

Min. Value Max. Value

Unit

CTNX Output Valid after CLKOUT Rising Edge (Output Delay)

tCANOV

—

26.0

CNRX Input Valid to CLKOUT Rising Edge (Setup Time)

tCANSU

—9.8

IRQ

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