EP3C55 datasheet(91/274 Pages) ALTERA

91 / 274 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–31

PLL Reconfiguration

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Bypassing PLL Counter

Bypassing a PLL counter results in a multiply (M counter) or a divide (N, C0 to C4

counters) factor of one.

Table 5–8 lists the settings for bypassing the counters in Cyclone III device family

PLLs.

To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits

are then ignored.

Dynamic Phase Shifting

The dynamic phase shifting feature allows the output phase of individual PLL

outputs to be dynamically adjusted relative to each other and the reference clock

without sending serial data through the scan chain of the corresponding PLL. This

feature simplifies the interface and allows you to quickly adjust tCO delays by

changing output clock phase shift in real time. This is achieved by incrementing or

decrementing the VCO phase-tap selection to a given C counter or to the M counter.

The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active

during this phase reconfiguration process.

Table 5–9 lists the control signals that are used for dynamic phase shifting.

Table 5–7. Loop Filter Control of High Frequency Capacitor

LFC[1]

LFC[0]

Setting (Decimal)

Table 5–8. PLL Counter Settings

PLL Scan Chain Bits [0..8] Settings

Description

LSB

MSB

1 (1)

PLL counter bypassed

0 (1)

PLL counter not bypassed

Note to Table 5–8:

(1) Bypass bit.

Table 5–9. Dynamic Phase Shifting Control Signals (Part 1 of 2)

Signal Name

Description

Source

Destination

PHASECOUNTERSELECT[2:0]

Counter Select. Three bits decoded to select

either the M or one of the C counters for

phase adjustment. One address map to select

all C counters. This signal is registered in the

PLL on the rising edge of SCANCLK.

Logic array or I/O

pins

PLL

reconfiguration

circuit

PHASEUPDOWN

Selects dynamic phase shift direction; 1= UP,

0 = DOWN. Signal is registered in the PLL on

the rising edge of SCANCLK.

Logic array or I/O

pins

PLL

reconfiguration

circuit

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