MPC8358ECVRADDDA datasheet(88/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

QUICC Engine Block PLL Configuration

The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in this table.

NOTE

The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine

block VCO frequency is in the range of 600–1400 MHz. The QUICC Engine block

frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC

Engine block frequencies should be selected according to the performance requirements.

11101

× 29

11110

× 30

11111

× 31

00011

× 1.5

00101

× 2.5

00111

× 3.5

01001

× 4.5

01011

× 5.5

01101

× 6.5

01111

× 7.5

10001

× 8.5

10011

× 9.5

10101

× 10.5

10111

× 11.5

11001

× 12.5

11011

× 13.5

11101

× 14.5

Note:

1. Reserved modes are not listed.

Table 75. QUICC Engine Block PLL VCO Divider

RCWL[CEVCOD]

VCO Divider

Reserved

Table 74. QUICC Engine Block PLL Multiplication Factors (continued)

RCWL[CEPMF] RCWL[CEPDF]

QUICC Engine PLL

Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF])

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