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MCP4341502E/ML 데이터시트(PDF) 45 Page - Microchip Technology

부품명 MCP4341502E/ML
상세설명  7/8-Bit Quad SPI Digital POT with Non-Volatile Memory
PDF  80 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP4341502E/ML 데이터시트(HTML) 45 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS22233A-page 45
MCP434X/436X
6.2
The SPI Modes
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.2.1
MODE 0,0
In Mode 0,0: SCK idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
6.2.2
MODE 1,1
In Mode 1,1: SCK idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
6.3
SPI Waveforms
Figure 6-2 through Figure 6-5 show the different SPI
command waveforms. Figure 6-2 and Figure 6-3 are
read and write commands. Figure 6-4 and Figure 6-5
are increment and decrement commands. The high
voltage increment and decrement commands are used
to enable and disable WiperLock Technology and Write
Protect.
FIGURE 6-2:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
FIGURE 6-3:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
CS
SCK
Write to
SSPBUF
SDI
Input
Sample
SDO
bit15 bit14 bit13 bit12 bit11
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15 bit14 bit13 bit12
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AD3
AD2
AD1
AD0
C1
C0
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
VIH
VIL
CMDERR bit
VIHH
CS
SCK
Write to
SSPBUF
SDI
Input
Sample
SDO
bit15
bit14 bit13 bit12 bit11
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit15 bit14 bit13 bit12
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AD3
AD2
AD1
AD0
C1
C0
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
VIH
VIL
CMDERR bit
VIHH



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