전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

MCP41010E/P 데이터시트(PDF) 22 Page - Microchip Technology

부품명 MCP41010E/P
상세설명  Single/Dual Digital Potentiometer with SPI Interface
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP41010E/P 데이터시트(HTML) 22 Page - Microchip Technology

Back Button MCP41010E/P Datasheet HTML 18Page - Microchip Technology MCP41010E/P Datasheet HTML 19Page - Microchip Technology MCP41010E/P Datasheet HTML 20Page - Microchip Technology MCP41010E/P Datasheet HTML 21Page - Microchip Technology MCP41010E/P Datasheet HTML 22Page - Microchip Technology MCP41010E/P Datasheet HTML 23Page - Microchip Technology MCP41010E/P Datasheet HTML 24Page - Microchip Technology MCP41010E/P Datasheet HTML 25Page - Microchip Technology MCP41010E/P Datasheet HTML 26Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 32 page
background image
MCP41XXX/42XXX
DS11195C-page 22
 2003 Microchip Technology Inc.
5.8
Using the MCP41XXX/42XXX in
SPI Mode 1,1
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
FIGURE 5-5:
Timing Diagram for SPI Mode 1,1 Operation.
SO‡
SI
SCK
CS†
23
456
7
8
9
10
1
New Register Data
D7
D6
D5
D4
D3
D2
D1
D0
P1* P0
11
12
13
14
15
16
X
C1
C0
X
X
X
Channel
Select
Bits
Data Registers are
loaded on rising
edge of CS. Shift
First 16 bits Shifted out will always be zeros
Don’t
Care
Bits
Command
Bits
Don’t
Care
Bits
† There must always be multiples of 16 clocks while CS is low or commands will abort.
‡ The serial data out pin (SO) is only available on the MCP42XXX device.
COMMAND BYTE
DATA BYTE
X
register is loaded
with zeros at this time.
Data is always latched in
on the rising edge of SCK.
Data is always clocked out the SO
pin after the falling edge of SCK.
SO pin will always
drive low when CS
goes high.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com