PIC18F1220ESLASHSSSQTP datasheet(186/308 Pages) MICROCHIP

186 / 308 page

PIC18F1220/1320

DS39605F-page 184

19.4.4

POR OR WAKE FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or Low-Power Sleep mode. When the primary

system clock is EC, RC or INTRC modes, monitoring

can begin immediately following these events.

For oscillator modes involving a crystal or resonator

(HS, HSPLL, LP or XT), the situation is somewhat dif-

ferent. Since the oscillator may require a start-up time

considerably longer than the FCSM sample clock time,

a false clock failure may be detected. To prevent this,

the internal oscillator block is automatically configured

as the system clock and functions until the primary

clock is stable (the OST and PLL timers have timed

out). This is identical to Two-Speed Start-up mode.

Once the primary clock is stable, the INTRC returns to

its role as the FSCM source

As noted in Section 19.3.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock configuration and enter an alter-

nate power managed mode while waiting for the

primary system clock to become stable. When the new

powered managed mode is selected, the primary clock

is disabled.

Note:

The same logic that prevents false oscilla-

tor failure interrupts on POR or wake from

Sleep will also prevent the detection of the

oscillator’s failure to start at all following

these events. This can be avoided by

monitoring the OSTS bit and using a

timing routine to determine if the oscillator

is taking too long to start. Even so, no

oscillator failure interrupt will be flagged.

PIC18F1220E/SSSQTP 데이터시트(PDF) 186 Page - Microchip Technology