2

2467XS–AVR–06/11

ATmega128

Pin

Configurations

Figure 1. Pinout ATmega128

Note:

The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF

package should be soldered to ground.

Overview

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PEN

RXD0/(PDI) PE0

(TXD0/PDO) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

(ICP3/INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC0) PB4

(OC1A) PB5

(OC1B) PB6

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PG2(ALE)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PG1(RD)

PG0(WR)