AD7671

–18–

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

12

3

14

15

16

D15

D14

D2

D1

D0

X

EXT/

INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

Figure 17. Master Serial Data Timing for Reading (Read after Convert)

EXT/

INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

12

3

14

15

16

BUSY

SYNC

SCLK

SDOUT

CS, RD

CNVST

Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

MASTER SERIAL INTERFACE

Internal Clock

The AD7671 is configured to generate and provide the serial data

clock SCLK when the EXT/

INT pin is held LOW. It also gener-

ates a SYNC signal to indicate to the host when the serial data is

valid. The serial clock SCLK and the SYNC signal can be inverted

if desired. Depending on RDC/SDIN input, the data can be read

after each conversion or during conversion. Figures 17 and 18

show the detailed timing diagrams of these two modes.

Usually, because the AD7671 is used with a fast throughput, the

mode master, read during conversion, is the most recommended

Serial Mode when it can be used.

In Read-during-Conversion Mode, the serial clock and data toggle

at appropriate instants, which minimizes potential feedthrough

between digital activity and the critical conversion decisions.

In Read-after-Conversion Mode, it should be noted that unlike

in other modes, the signal BUSY returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

While the AD7671 is performing a bit decision, it is important that

voltage transients not occur on digital input/output pins or degra-

dation of the conversion result could occur. This is particularly

important during the second half of the conversion phase because

REV. C